With respect to FIG. 1, a prior art multiplexer circuit 100, from U.S. Pat. No. 5,701,095 to Ohsawa includes a data selecting circuit 110 and an NMOS pre-charge transistor 120. Input data signals A through D and select signals āthrough d(a-bar through d-bar) control the connection of a system supply potential VDD to a common node X providing an output signal Q (Q-bar) by biasing the gate terminals of PMOS transistors 2-1 thru 2-4 and 3-1 thru 3-4. The common node X is charged to a system round potential GND by setting a pre-charge signal PRCH high, thereby biasing the NMOS pre-charge transistor 120 into conduction. After completion of the charging operation, the pre-charge signal PRCH goes low, and the common node X floats. The '095 patent discloses a method for setting the input data signals A-D at a level lower than the power supply voltage VDD to speed up transmission of the input data signals A-D to the common node X. However, the '095 patent does not disclose control of the pre-charge potential at the common node X as a method to speed up the transmission of the input, data signals A-D to the common node X.